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rvdbg User Guide

中文

rvdbg uses one rvdbg.toml to flash, debug and inspect rustvisor boards. With a Lauterbach probe it uses TRACE32 PowerView; with StellarLINK it runs openocd-stellar as a separate process. Build firmware with your project’s own build system: rvdbg deploys existing images and helps inspect the target.

This guide covers Apple Silicon macOS and Linux x86_64/aarch64 hosts. The board defaults generated by rvdbg init target SR6P6. Before using another board, check scripts, core names, memory access ports and OTP ranges.

Start with your task

TaskReadExpected outcome
First useQuick startInstall dependencies, configure, flash and inspect
Change images, probes or coresConfigurationIdentify effective images, backend and ports
Update code or symbolsFlashing and verificationChoose flash/load and handle multiple images
Breakpoints and steppingDebuggingConnect an IDE/GDB and understand target state changes
Diagnose a running programInspectionInspect PC, faults, memory, clocks and acceptance conditions
Logs and packetsRTT and FDXLocate buffers and choose a transport
Scripts and agentsAutomationInterpret JSON, exit codes and session boundaries
Failed operationsTroubleshootingFind the next check from the symptom

Follow the table in order on your first visit; use task pages directly afterwards. Standard Markdown relative links work in GitHub and Obsidian. The mdBook website adds “Referenced by” sections to show which pages depend on the current page.

Backend differences

CapabilityTRACE32StellarLINK / OpenOCD
Flash, verify, status, halt and resumeSupportedSupported
IDEsVS Code and RustRover/LSP4IJ over DAPVS Code/Cortex-Debug and GDB
Ordinary RAM, RTT and FDXRuntime access through AD:Runtime access through MEM-AP
Debug symbolsrvdbg loadGDB reads the ELF
PER register namesreg, watchUse addresses or check files instead
PRACTICEeval, cmd, doUnsupported
Trace exporttrace, fault --traceUnsupported
Clock diagramclock --htmlText/JSON tree only

Shared command names do not imply that every option works on both backends. See configuration for selection and individual task pages for restrictions.

Understand what an operation changes

Inspection commands such as status, mem, fault, verify and check without --halt do not automatically reset or halt the target to obtain a value. Some register reads will therefore fail. Distinguish ordinary RAM from MMIO with read side effects; see inspection.

flash writes Flash and resets the target; reset resets and halts it. halt, go and run-until change execution state. load loads symbols and resumes when necessary. IDE connection can also execute board reset hooks; see debugging.

ram --write changes target RAM. FDX sends can trigger firmware actions. cmd and do depend on the PRACTICE content and can perform arbitrary target operations.

Use rvdbg --help and rvdbg <command> --help for full arguments. This guide explains workflows and interpretation; consult your installed version’s help and rvdbg init output for defaults. See maintaining this guide for local previews and link conventions.